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low voltage 1.65 v to 3.6 v, bidirectional logic level translation, bypass switch adg3233 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2003C2011 analog devices, inc. all rights reserved. features operates from 1.65 v to 3.6 v supply rails bidirectional level translation, unidirectional signal path 8-lead sot-23 and msop packages bypass or normal operation short circuit protection applications jtag chain bypassing daisy-chain bypassing digital switching functional block diagram a1 y1 y2 a2 gnd adg3233 v cc1 v cc2 v cc1 v cc1 v cc1 v cc2 v cc2 en 0 1 03297-001 figure 1. general description the adg3233 1 is a bypass switch designed on a submicron process that operates from supplies as low as 1.65 v. the device is guaranteed for operation over the supply range 1.65 v to 3.6 v. it operates from two supply voltages, allowing bidirectional level translation, that is, it translates low voltages to higher voltages and vice versa. the signal path is unidirectional, meaning data may only flow from a y. this type of device may be used in applications that require a bypassing function. it is ideally suited to bypassing devices in a jtag chain or in a daisy-chain loop. one switch could be used for each device or a number of devices, thus allowing easy bypassing of one or more devices in a chain. this may be particularly useful in reducing the time overhead in testing devices in the jtag chain or in daisy-chain applications where the user does not wish to change the settings of a particular device. the bypass switch is packaged in two of the smallest footprints available for its required pin count. the 8-lead sot-23 package requires only 2.9 mm 2.8 mm board space, while the msop package occupies approximately 3 mm 4.9 mm board area. product highlights 1. bidirectional level translation matches any voltage level from 1.65 v to 3.6 v. 2. the bypass switch offers high performance and is fully guaranteed across the supply range. 3. short circuit protection. 4. tiny 8-lead sot-23 package and 8-lead msop. table 1. truth table en signal path function l a1 y2, y1 v cc1 enable bypass mode h a1 y2, a2 y2 enable normal mode 1 u.s. patent number: 7,369,385 b2.
adg3233 rev. a | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 test waveforms ............................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution...................................................................................6 pin configuration and function descriptions ..............................7 typical performance characteristics ..............................................8 theory of operation ...................................................................... 13 a1 and en input ........................................................................ 13 normal operation ...................................................................... 13 bypass operation ....................................................................... 14 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 16 revision history 7 /11rev. 0 to rev. a changes to patent number, general description section, and product highlights section ............................................................. 1 changes to v cc = v cc1 = v cc2 = 2.5 v 0.2 v, enable time en y1, table 2 ............................................................................. 4 changes to table 3 ............................................................................ 6 updated outline dimensions ....................................................... 15 changes to ordering guide .......................................................... 16 5/03revision 0: initial version
adg3233 rev. a | page 3 of 16 specifications v cc1 = v cc2 = 1.65 v to 3.6 v, gnd = 0 v, all specifications t min to t max , unless otherwise noted. table 2. parameter 1 symbol test conditions/comments min typ 2 max unit logic inputs/outputs 3 v cc2 = 1.65 v to 3.6 v, gnd = 0 v input high voltage 4 v ih v cc1 = 3.0 v to 3.6 v 1.35 v v cc1 = 2.3 v to 2.7 v 1.35 v v cc1 = 1.65 v to 1.95 v 0.65 v cc v input low voltage 4 v il v cc1 = 3.0 v to 3.6 v 0.8 v v cc1 = 2.3 v to 2.7 v 0.7 v v cc1 = 1.65 v to 1.95 v 0.35 v cc v output high voltage (y1) v oh i oh = ?100 a, v cc1 = 3.0 v to 3.6 v 2.4 v i oh = ?100 a, v cc1 = 2.3 v to 2.7 v 2.0 v i oh = ?100 a, v cc1 = 1.65 v to 1.95 v v cc ? 0.45 v i oh = ?4 ma, v cc1 = 2.3 v to 2.7 v 2.0 v i oh = ?4 ma, v cc1 = 1.65 v to 1.95 v v cc C 0.45 v i oh = ?8 ma, v cc1 = 3.0 v to 3.6 v 2.4 v output low voltage (y1) v ol i ol = 100 a, v cc1 = 3.0 v to 3.6 v 0.40 v i ol = 100 a, v cc1 = 2.3 v to 2.7 v 0.40 v i ol = 100 a, v cc1 = 1.65 v to 1.95 v 0.45 v i ol = 4 ma, v cc1 = 2.3 v to 2.7 v 0.40 v i ol = 4 ma, v cc1 = 1.65 v to 1.95 v 0.45 v i ol = 8 ma, v cc1 = 3.0 v to 3.6 v 0.40 v logic outputs 3 v cc1 = 1.65 v to 3.6 v, gnd = 0 v output high voltage (y2) v oh i oh = ?100 a, v cc2 = 3.0 v to 3.6 v 2.4 v i oh = ?100 a, v cc2 = 2.3 v to 2.7 v 2.0 v i oh = ?100 a, v cc2 = 1.65 v to 1.95 v v cc ? 0.45 v i oh = ?4 ma, v cc2 = 2.3 v to 2.7 v 2.0 v i oh = ?4 ma,v cc2 = 1.65 v to 1.95 v v cc C 0.45 v i oh = ?8 ma, v cc2 = 3.0 v to 3.6 v 2.4 v output low voltage (y2) v ol i ol = 100 a, v cc2 = 3.0 v to 3.6 v 0.40 v i ol = 100 a, v cc2 = 2.3 v to 2.7 v 0.40 v i ol = 100 a, v cc2 = 1.65 v to 1.95 v 0.45 v i ol = 4 ma, v cc2 = 2.3 v to 2.7 v 0.40 v i ol = 4 ma, v cc2 = 1.65 v to 1.95 v 0.45 v i ol = 8 ma, v cc2 = 3.0 v to 3.6 v 0.40 v switching characteristics 4, 5 v cc = v cc1 = v cc2 = 3.3 v 0.3 v propagation delay, t pd a1 y1 normal mode t phl , t plh c l = 30 pf, v t = v cc /2 3.5 5.4 ns a2 y2 normal mode t phl , t plh c l = 30 pf, v t = v cc /2 3.5 5.4 ns a1 y2 bypass mode t phl , t plh c l = 30 pf, v t = v cc /2 4 6.5 ns enable time en y1 t en c l = 30 pf, v t = v cc /2 4 6 ns disable time en y1 t dis c l = 30 pf, v t = v cc /2 2.8 4 ns enable time en y2 t en c l = 30 pf, v t = v cc /2 4.5 6.5 ns disable time en y2 t dis c l = 30 pf, v t = v cc /2 4 6.5 ns
adg3233 rev. a | page 4 of 16 parameter 1 symbol test conditions/comments min typ 2 max unit v cc = v cc1 = v cc2 = 2.5 v 0.2 v propagation delay, t pd a1 y1 normal mode t phl , t plh c l = 30 pf, v t = v cc /2 4.5 6.2 ns a2 y2 normal mode t phl , t plh c l = 30 pf, v t = v cc /2 4.5 6.2 ns a1 y2 bypass mode t phl , t plh c l = 30 pf, v t = v cc /2 4.5 6.5 ns enable time en y1 t en c l = 30 pf, v t = v cc /2 5 7.2 ns disable time en y1 t dis c l = 30 pf, v t = v cc /2 3.2 4.7 ns enable time en y2 t en c l = 30 pf, v t = v cc /2 5 7.7 ns disable time en y2 t dis c l = 30 pf, v t = v cc /2 4.8 7.2 ns v cc = v cc1 = v cc2 = 1.8 v 0.15 v propagation delay, t pd a1 y1 normal mode t phl , t plh c l = 30 pf, v t = v cc /2 6.7 10 ns a2 y2 normal mode t phl , t plh c l = 30 pf, v t = v cc /2 6.5 10 ns a1 y2 bypass mode t phl , t plh c l = 30 pf, v t = v cc /2 6.5 10.25 ns enable time en y1 t en c l = 30 pf, v t = v cc /2 7 10.5 ns disable time en y1 t dis c l = 30 pf, v t = v cc /2 4.4 6.5 ns enable time en y2 t en c l = 30 pf, v t = v cc /2 7 12 ns disable time en y2 t dis c l = 30 pf, v t = v cc /2 6.5 10.5 ns input leakage current i i 0 v in 3.6 v 1 a output leakage current i o 0 v in 3.6 v 1 a power requirements power supply voltages v cc1 1.65 3.6 v v cc2 1.65 3.6 v quiescent power supply current i cc1 digital inputs = 0 v or v cc 2 a i cc2 digital inputs = 0 v or v cc 2 a increase in i cc per input i cc1 v cc = 3.6 v, one input at 3.0 v; others at v cc or gnd 0.75 a 1 temperature range is as follows: b version: ?40c to +85c. 2 all typical values are at v cc = v cc1 = v cc2 , t a = 25c, unless otherwise stated. 3 v il and v ih levels are specified with respect to v cc1 , v oh , and v ol levels for y1 are specified with respect to v cc1 , and v oh , and v ol levels are specified for y2 with respect to v cc2 . 4 guaranteed by design, not subject to production test. 5 see the test waveforms section.
adg3233 rev. a | page 5 of 16 test waveforms input output v cc1 0v v t t plh t phl v t v oh v ol 03297-032 figure 2. propagation delay en y1 (a1 at gnd) v cc1 0v v t v t v t t dis t en v oh v ol 03297-033 figure 3. y1 enable and disable times en a1 v cc1 v cc1 v cc1 0v 0v 0v v t v t t dis t en v t v ol v olh 03297-034 a2 y2 figure 4. y2 enable and disable times
adg3233 rev. a | page 6 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v cc to gnd C0.3 v to +4.6 v digital inputs to gnd C0.3 v to +4.6 v a1, en C0.3 v to +4.6 v a2 C0.3 v to v cc1 + 0.3 v dc output current 25 ma operating temperature range industrial (b version) C40c to +85c storage temperature range C65c to +150c junction temperature 150c 8-lead msop ja thermal impedance 206c/w jc thermal impedance 43c/w 8-lead sot-23 ja thermal impedance 211c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature (<20 sec) 235c soldering (pb-free) reflow, peak temperature 260(+0/?5)c time at peak temperature 20 sec to 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. esd caution
adg3233 rev. a | page 7 of 16 pin configuration and fu nction descriptions v cc1 1 a1 2 a2 3 en 4 v cc2 8 y1 7 y2 6 gnd 5 adg3233 top view (not to scale) 03297-002 figure 5. 8-lead sot-23 package (rj-8) en v cc2 1 y1 2 y2 3 gnd 4 v cc1 8 a1 7 a2 6 5 adg3233 top view (not to scale) 03297-003 figure 6. 8-lead msop package (rm-8) table 4. pin function descriptions pin no. rj-8 rm-8 mnemonic description 1 8 v cc1 supply voltage 1, can be any supply voltage from 1.65 v to 3.6 v. 8 1 v cc2 supply voltage 2, can be any supply voltage from 1.65 v to 3.6 v. 2 7 a1 input referred to v cc1 . 3 6 a2 input referred to v cc2 . 7 2 y1 output referred to v cc1 . 6 3 y2 output referred to v cc2 . voltage levels appearing at y2 will be translated from a v cc1 voltage level to a v cc2 voltage level. 4 5 en active low device enable. when low, bypass mode is enabled; when high, the device is in normal mode. 5 4 gnd device ground.
adg3233 rev. a | page 8 of 16 typical performance characteristics 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 v cc1 (v) i cc1 (na) 3.5 4.0 t a = 25c v cc2 = 2.5v v cc2 = 1.8v v cc2 = 3.3v 03297-004 figure 7. i cc1 vs. v cc1 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 v cc2 (v) i cc2 (na) 3.5 4.0 t a = 25c v cc1 = 2.5v v cc1 = 1.8v v cc1 = 3.3v 03297-005 figure 8. i cc2 vs. v cc2 30 25 20 15 10 5 0 0 1020304050607080 temperature (c) i cc1 (na) v cc2 = 3.3v v cc1 = 2.5v v cc1 = 3.3v v cc1 = 1.8v 03297-006 figure 9. i cc1 vs. temperature 30 25 20 15 10 0 ?5 5 0 1020304050607080 temperature (c) i cc2 (na) v cc1 = 3.3v v cc2 = 3.3v v cc2 = 2.5v v cc2 = 1.8v 03297-007 figure 10. i cc2 vs. temperature 2000 1800 1600 1400 1200 1000 800 600 400 200 0 10k 100k 1m 10m 100m i cc1 (a) frequency (hz) t a = 25c v cc1 = v cc2 = 3.3v v cc1 = v cc2 = 1.8v 03297-008 figure 11. i cc1 vs. frequency, normal mode 80 70 60 50 40 30 20 10 0 10k 100k 1m 10m 100m i cc1 (a) frequency (hz) t a = 25c v cc1 = v cc2 = 3.3v v cc1 = v cc2 = 1.8v 03297-009 figure 12. i cc1 vs. frequency, bypass mode
adg3233 rev. a | page 9 of 16 2000 1800 1600 1400 1200 1000 800 600 400 200 0 10k 100k 1m 10m 100m i cc2 (a) frequency (hz) t a = 25c v c c 1 = v c c 2 = 3 . 3 v v cc1 = v cc2 = 1.8v 03297-010 figure 13. i cc2 vs. frequency, normal mode 2000 1800 1600 1400 1200 1000 800 600 400 200 0 10k 100k 1m 10m 100m i cc2 (a) frequency (hz) t a = 25c v c c 1 = v c c 2 = 3 .3 v v cc1 = v cc2 = 1.8v 03297-011 figure 14. i cc2 vs. frequency, bypass mode 10 8 6 4 2 1.5 2.0 2.5 supply (v) time (ns) 3.0 3.5 4.0 0 t dis t en t a = 25c v cc1 = v cc2 03297-012 figure 15. y1 enable, disable time vs. supply 10 8 6 4 2 1.5 2.0 2.5 supply (v) time (ns) 3.0 3.5 4.0 0 t dis t a = 25c v cc1 = v cc2 03297-013 t en figure 16. y2 enable, disable time vs. supply 6 4 5 3 2 1 ?40 ?20 0 temperature (c) time (ns) 20 40 60 80 0 t dis v cc1 = v cc2 = 3.3v 03297-014 t en figure 17. y1 enable, disable time vs. temperature 6 4 5 3 2 1 ?40 ?20 0 temperature (c) time (ns) 20 40 60 80 0 t dis v cc1 = v cc2 = 3.3v 03297-015 t en figure 18. y2 enable, disable time vs. temperature
adg3233 rev. a | page 10 of 16 16 14 10 6 2 12 8 4 22 32 52 62 42 capacitive load (pf) rise/fall time (ns) 72 82 92 102 0 v cc1 = 3.3v v cc2 = 1.8v t a = 25c data rate = 10mbps t plh, low-to-high transition t phl, high-to-low transition 03297-016 figure 19. rise/fall time vs. capacitive load, a1 y1, a2 y2 16 14 10 6 2 12 8 4 22 32 52 62 42 capacitive load (pf) rise/fall time (ns) 72 82 92 102 0 t plh, low-to-high transition t phl, high-to-low transition v cc1 = 3.3v v cc2 = 1.8v t a = 25c data rate = 10mbps 03297-017 figure 20. rise/fall time vs. capacitive load, a1 y2, bypass mode 10 9 5 3 1 7 8 6 4 2 22 32 52 62 42 capacitive load (pf) rise/fall time (ns) 72 82 92 102 0 v cc1 = 1.8v v cc2 = 3.3v t a = 25c data rate = 10mbps t plh , low-to-high transition t phl , high-to-low transition 03297-018 figure 21. rise/fall time vs. capacitive load, a1 y1, a2 y2 10 9 5 3 1 7 8 6 4 2 22 32 52 62 42 capacitive load (pf) rise/fall time (ns) 72 82 92 102 0 v cc1 = 1.8v v cc2 = 3.3v t a = 25c data rate = 10mbps t plh , low-to-high transition t phl , high-to-low transition 03297-019 figure 22. rise/fall time vs. capacitive load, a1 y2, bypass mode 5 3 1 7 8 6 4 2 22 32 52 62 42 capacitive load (pf) propa g a tion del a y (ns) 72 82 92 102 0 v cc1 = 3.3v v cc2 = 3.3v t a = 25c data rate = 10mbps 03297-020 t plh , low-to-high transition t phl , high-to-low transition figure 23. propagation delay vs. capacitive load a1 y1 5 3 1 7 8 6 4 2 22 32 52 62 42 capacitive load (pf) propa g a tion del a y (ns) 72 82 92 102 0 v cc1 = 3.3v v cc2 = 3.3v t a = 25c data rate = 10mbps 03297-021 t plh , low-to-high transition t phl , high-to-low transition figure 24. propagation delay vs. capacitive load a2 y2
adg3233 rev. a | page 11 of 16 5 3 1 7 8 6 4 2 22 32 52 62 42 capacitive load (pf) propa g a tion del a y (ns) 72 82 92 102 0 v cc1 = 3.3v v cc2 = 3.3v t a = 25c data rate = 10mbps 03297-022 t plh , low-to-high transition t phl , high-to-low transition figure 25. propagation delay vs. capacitive load a1 y2, bypass mode 5 3 1 7 8 6 4 2 1.5 2.0 2.5 3.0 3.5 supply (v) propa g a tion del a y (ns) 4.0 0 v cc1 = v cc2 t a = 25c 03297-023 t plh , a1 y1 t phl , a2 y2 t phl , a1 y1 t plh , a2 y2 figure 26. propagation delay vs. supply, normal mode 8 6 4 2 1.5 2.0 2.5 3.0 3.5 supply (v) propa g a tion del a y (ns) 4.0 0 v cc1 = v cc2 t a = 25c 03297-024 t phl , a1 y2 t plh , a1 y2 figure 27. propagation delay vs. supply, bypass mode ?40 ?20 0 temperature (c) 20 40 60 80 03297-025 v cc1 = v cc2 = 3.3v t plh , a1 y1 t phl , a2 y2 2.5 1.5 0.5 3.5 4.0 3.0 2.0 1.0 propa g a tion del a y (ns) 0 t plh , a2 y2 t phl , a1 y1 figure 28. propagation delay vs. temperature, normal mode ?40 ?20 0 temperature (c) 20 40 60 80 03297-026 v cc1 = v cc2 = 3.3v 4 3 2 1 propa g a tion del a y (ns) 0 t phl , a1 y2 t plh , a1 y2 figure 29. propagation delay vs. temperature, bypass mode ch1 1.00v ch2 500mv ch3 1.00v ? ch4 1.00v ? m5.00ns ch1 1.48v 3 2 4 1 en = high t a = 25c data rate = 10mhz a1 y1 3.3v 3.3v 1.8v a2 y2 03297-027 figure 30. normal mode v cc1 = 3.3 v, v cc2 = 1.8 v
adg3233 rev. a | page 12 of 16 ch2 1.00v ? ch2 500mv m5.00ns ch2 1.47v 3 2 a1 3.3v 1.8v y2 03297-028 data rate = 10mhz t a = 25c figure 31. bypass mode, v cc1 = 3.3 v, v cc2 = 1.8 v ch1 1.00v ch2 2.00v ch3 5.00v ? ch4 1.00v ? m5.00ns ch1 1.48v 3 2 4 1 data rate = 10mhz t a = 25c a1 y1 3.3v 3.3v 1.8v 1.8v a2 y2 03297-029 figure 32. normal mode, v cc1 = 1.8 v, v cc2 = 3.3 v ch1 1.00v ch2 2.00v ch3 1.00v ? m5.00ns ch3 900mv 3 2 1 data rate = 10mhz t a = 25c a1 y2 y1 3.3v 1.8v 1.8v 03297-030 figure 33. bypass mode, v cc1 = 1.8 v, v cc2 = 3.3 v 05 current (ma) 10 15 20 03297-031 v cc = 3.3v v cc = 3.3v v cc = 2.5v v cc = 2.5v v cc = 1.8v v cc = 1.8v source sink 2.5 1.5 0.5 3.5 3.0 2.0 1.0 voltage (v) 0 v cc = v cc1 = v cc2 t a = 25c figure 34. y1 and y2 source and sink current
adg3233 rev. a | page 13 of 16 theory of operation the adg3233 is a bypass switch designed on a submicron process that operates from supplies as low as 1.65 v. the device is guaranteed for operation over the supply range 1.65 v to 3.6 v. it operates from two supply voltages, allowing bidirectional level translation, that is, it translates low voltages to higher voltages and vice versa. the signal path is unidirectional, meaning data may only flow from a y. a1 and en input the a1 and enable ( en ) inputs have v il /v ih logic levels so that the part can accept logic levels of v ol /v oh from device 0 or the controlling device independent of the value of the supply being used by the controlling device. these inputs (a1, en ) are capable of accepting inputs outside the v cc1 supply range. for example, the v cc1 supply applied to the bypass switch could be 1.8 v while device 0 could be operating from a 2.5 v or 3.3 v supply rail, there are no internal diodes to the supply rails, so the device can handle inputs above the supply but inside the absolute maximum ratings. normal operation figure 35 shows the bypass switch being used in normal mode. in this mode, the signal paths are from a1 y1 and a2 y2. the device will level translate the signal applied to a1 to a v cc1 logic level (this level translation can be either to a higher or lower supply) and route the signal to the y1 output, which will have standard v ol /v oh levels for v cc1 supplies. the signal is then passed through device 1 and back to the a2 input pin of the bypass switch. the logic level inputs of a2 are with respect to the v cc1 supply. the signal will be level translated from v cc1 to v cc2 and routed to the y2 output pin of the bypass switch. y2 output logic levels are with respect to the v cc2 supply. v cc2 v cc1 v cc0 signal input a1 a2 y1 y2 logic 1 signal output device 0 device 1 device 2 v cc2 v cc1 03297-035 en bypass switch figure 35. bypass switch in normal mode
adg3233 rev. a | page 14 of 16 bypass operation figure 36 illustrates the device as used in bypass mode. the signal path is now from a1 directly to y2, thus bypassing device 1 completely. the signal will be level translated to a v cc2 logic level and available on y2, where it may be applied directly to the input of device 2. in bypass mode, y1 is pulled up to v cc1 . the three supplies in figure 35 and figure 36 may be any combination of supplies, that is., v cc0 , v cc1 , and v cc2 may be any combination of supplies, for example, 1.8 v, 2.5 v, and 3.3 v. v cc2 v cc1 v cc0 signal input en a1 a2 y1 y2 logic 0 signal output device 0 device 1 bypass switch device 2 v cc2 v cc1 03297-036 figure 36. bypass switch in bypass mode
adg3233 rev. a | page 15 of 16 outline dimensions compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 37. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters compliant to jedec standards mo-178-ba 8 4 0 seating plane 1.95 bsc 0.65 bsc 0.60 bsc 76 1234 5 3.00 2.90 2.80 3.00 2.80 2.60 1.70 1.60 1.50 1.30 1.15 0.90 0 .15 max 0 .05 min 1.45 max 0.95 min 0.22 max 0.08 min 0.38 max 0.22 min 0.60 0.45 0.30 pin 1 indicator 8 12-16-2008-a figure 38. 8-lead small outline transistor package [sot-23] (rj-8) dimensions shown in millimeters
adg3233 rev. a | page 16 of 16 ordering guide model 1 temperature range package description branding package option adg3233brj-reel ?40c to +85c 8-lead sot-23 w1b rj-8 adg3233brj-reel7 ?40c to +85c 8-lead sot-23 w1b rj-8 adg3233brjz-reel7 ?40c to +85c 8-lead sot-23 s1s rj-8 adg3233brm ?40c to +85c 8-lead msop w1b rm-8 adg3233brm-reel ?40c to +85c 8-lead msop w1b rm-8 adg3233brm-reel7 ?40c to +85c 8-lead msop w1b rm-8 adg3233brmz ?40c to +85c 8-lead msop s1s rm-8 ADG3233BRMZ-REEL7 ?40c to +85c 8-lead msop s1s rm-8 1 z = rohs compliant part. ?2003C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03297-0-7/11(a)

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